Dr. Archana Pandey

Education

• PhD, Title: “Impact of FinFET Parasitic Effects in Circuit Design”, Indian Institute of Technology, Roorkee
• M.Tech, Solid state Electronic Materials, Indian Institute of Technology, Roorkee
• B.Tech, Electronics & Communication Engineering, G. B. Pant Engineering College, Pauri

Research Area:

Novel semiconductor devices (FinFET, GAAFET, Nanosheet FET etc): device design, modelling and applications, VLSI device-circuit co-design, Negative capacitance FETs, VLSI-machine learning integration, FET sensors

Publications

International Journals:

• A. Pandey, S. Raycha, S. Maheshwaram, S. K. Manhas, S. Dasgupta, A. K. Saxena, and B. Anand, “Effect of load capacitance and input transition time on FinFET inverter capacitances,” IEEE Trans. Electron Devices, vol. 61, no. 1, pp. 30-36, 2014.
• A. Pandey, H. Kumar, S. K. Manhas, S. Dasgupta, and B. Anand, “Atypical Voltage transitions in FinFET Multi- Stage Circuits : Origin and Significance,” IEEE Transactions on Electron Devices, vol. 63, no. 3, pp. 1392-1396, March 2016.
• Archana Pandey, Recent Trends in Novel Semiconductor Devices. Silicon (2022):1-12. https://doi.org/10.1007/s12633-022-01694-8
• Mandeep Singh Narula, Archana Pandey, “Performance Evaluation of Stacked Gate Oxide/High K Spacers Based Gate All Around Device Architectures at 10 nm Technology Node”, Silicon (2022). https://doi.org/10.1007/s12633-022-01685-9
• Mandeep Singh Narula, Archana Pandey, “Gate Engineered Silicon Nanowire FET with Coaxial Inner Gate for Enhanced Performance” Silicon 15, 4217–4227 (2023). https://doi.org/10.1007/s12633-023-02340-7, Feb 2023 - Indexed in Science Citation Index Expanded (SCI) and SCOPUS, Impact factor – 2.941
• Mandeep Singh Narula, Archana Pandey, “Dual Gate Silicon Nanowire FET with Corner Spacer for High Performance & High Frequency Applications “Journal of Electronic Materials” 2023, https://doi.org/10.1007/s11664-023-10597-2.

International Conferences:

• A. Pandey, S. Raycha, S. Maheshwaram, S. K. Manhas, S. Dasgupta, A. K. Saxena, and B. Anand, “FinFET device capacitances: Impact of input transition time and output load,” in  Proc. IEEE 5th International Nanoelectronics Conference (INEC), Singapore, Jan. 2013, pp. 393-395.
• A. Pandey, H. Kumar, P. Goyal, S. Dasgupta, S. K. Manhas and B. Anand, “FinFET Device Circuit Co-design Issues : Impact of Circuit Parameters on Delay,” in Proc. IEEE VLSI Design, Kolkata, Jan. 2016, pp. 288-293.
• A. Pandey, P. Garg, S. Tyagi, R. Ranjan and B. Anand,  “A modified method of logical effort for FinFET circuits considering impact of fin-extension effects”  in Proc. 19th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, Mar. 2018, 189-195.
• Yash Sharma, Anushka Singh, and Archana Pandey, “Comparative Design and Analysis of FinFET and CMOS SRAM Cell,” IEEE International Conference on Signal Processing and Communication (ICSC), Noida, India, 7-9 March, 2019, 10.1109/ICSC45622.2019.8938343
• Sarita Yadav, Nitanshu Chauhan, Archana Pandey, Rajendra Pratap, and Bulusu  Anand. "Behaviour of FinFET Inverter’s Effective Capacitances in Low-Voltage Domain." 25th IEEE International Symposium on VLSI Design and Test (VDAT), Surat, India, pp. 1-5, 2021. doi: 10.1109/VDAT53777.2021.9601052
• M. S. Narula and A. Pandey, "A Comprehensive Review on FinFET, Gate All Around, Tunnel FET: Concept, Performance and Challenges," 8th International Conference on Signal Processing and Communication (ICSC), Noida, India, 2022, pp. 554-559, doi: 10.1109/ICSC56524.2022.10009504.

Book Chapter:

• Anushka Singh, and Archana Pandey. "Gate-All-Around Nanosheet FET Device Simulation Methodology Using a Sentaurus TCAD." Advanced Field-Effect Transistors. CRC Press, ISBN- 9781003393542, 2023. 232-259.
• Anushka Singh, Yash Sharma, Arvind Sharma, and Archana Pandey, “A Novel 20nm FinFET Based 10T SRAM Cell Design for Improved Performance” in Communications in Computer and Information Science book series (2019) pp. 523-531, Springer, Singapore, DOI: 10.1007/978- 981-32-9767- 8_43
• Saurabh K. Nema, M. SaiKiran (2), P. Singh (2), Archana Pandey (2), S. K. Manhas (2), A. K. Saxena (2), Anand Bulusu (2)“Improved Underlap FinFET with Asymmetric Spacer Permittivities” in Physics of Semiconductor Devices. Springer, Cham, DOI (Digital   ObjectIdentifier):10.1007/9783319030029_67.

Book:

1. Ekta Goel, Archana Pandey, "Nanoscale Field Effect Transistors: Emerging   Applications", Bentham Science Publishers(2023). https://doi.org/10.2174/97898151656471230101.

PhD Supervised:

1. PhD Supervision on the topic “Design and performance investigation of gate/channel engineered gate all around field effect transistor” Degree awarded in Oct 2023.
2. PhD Supervision on the topic “Nanoscale semiconductor FETs and their applications” is in progress.

M.Tech dissertation supervised: 3 Awarded

B. Tech Projects supervised: More than 20 B.Tech projects guided

Academic Achievements:

• Second position in state (Uttarakhand, India) in Intermediate Uttarakhand Board
• Got Merit scholarship in all the four years of B. Tech
• Qualified GATE examination with 99.08 percentile

Technical Exposure:

Simulation Tools: Experience of TCAD Sentaurus (Sentaurus structure editor, Sdevice, Sprocess, Tecplot, Svisual, Inspect), TSPICE, HSPICE, PSPICE, Silvaco Atlas