Jaypee Institute of Information Technology, Noida
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  • Dr. Shruti Kalra
Assistant Professor (Senior Grade)
shruti.kalra@jiit.ac.in

Education

PhD (Microelectronics), M.Tech (VLSI Design), B.Tech (Electronics and Communication)

Biography

Done B.Tech in Electronics and communication from UPTU in 2005,M.Tech in VLSI Design from CDAC, Noida in 2007 and PhD in Microelectronics from JIIT in 2018.

Joined Center for development of Advanced Computing (CDAC Noida)  in 2007 as a lecturer. In 2008, joined JIIT as a lecturer. Currently working as an Assistant Professor (Senior Grade) in department of Electronics and Communication at JIIT.

Work Experience

16  years (Teaching + Research)

Interest Area(s)

Full custom design, CMOS Digital VLSI Design.

Publications

International Journals:

  • R. Beniwal, S. Kalra, N. S. Beniwal, H. Mazumdar, A. K. Singhal, and S. K. Singh, "Walk-to-Charge Technology: Exploring Efficient Energy Harvesting Solutions for Smart Electronics," Journal of Sensors, vol. 2023, 2023.

  • K. Singh and S. Kalra, "Reliability forecasting and Accelerated Lifetime Testing in advanced CMOS technologies," Microelectronics Reliability, vol. 151, p. 115261, 2023.

  • K. Singh and S. Kalra, "A Machine Learning Based Reliability Analysis of Negative Bias Temperature Instability (NBTI) Compliant Design for Ultra Large Scale Digital Integrated Circuit Design," Journal of Integrated Circuits and Systems.

  • R. Beniwal, S. Kalra, N. Singh Beniwal, and H.O. Gupta, "Smart photovoltaic system for Indian smart cities: a cost analysis," Environmental Science and Pollution Research, pp. 1-10, 2023.

  • S. Kalra, "Neural Network Based Thermal Analysis of Ultradeep Submicron Digital Circuit Design," Journal of Harbin Institute of Technology (New Series), 2023. [Online]. Available: http://hit.alljournals.cn/jhit_cn/ch/reader/download_new_edit_content.as...

  • S. Kalra, "Design and Optimization of Ultradeep Submicron CMOS Inverter Using a Unified All Regional MOSFET Model," Journal of Integrated Circuits and Systems, vol. 17, no. 3, pp. 1-14, 2022.

  • S. Kalra, "Mathematical Insight into Moderate Inversion Gate Delay Variability for Ultradeep Submicron Digital Circuit Design," Journal of Harbin Institute of Technology (New Series), 2022. [Online]. Available: http://hit.alljournals.cn/jhit_cn/ch/reader/create_pdf.aspx?file_no=2023...

  • S. Kalra and R. Beniwal, "Analytical Modeling for Translating Statistical Changes to Circuit Variability by Ultra-Deep Submicron Digital Circuit Design," Journal of Harbin Institute of Technology (New Series), vol. 29, no. 4, pp. 70-80, 2022.

  • S. Kalra and R. Beniwal, "ANFIS Based Thermal Estimation of Ultradeep Submicron Digital Circuit Design," Journal of Integrated Circuits and Systems, vol. 16, no. 3, pp. 1-10, 2021.

  • Kalra, "An Insight into Temperature Inversion Using α-Power MOSFET Model for Ultradeep Submicron Digital CMOS Technologies," AEU-International Journal of Electronics and Communications, vol. 125, p. 153349, July 2020.

  • S. Kalra and A.B. Bhattacharyya, "A Unified Analytical Transregional MOSFET Model for Nanoscale CMOS Digital Technologies," International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol. 33, issue 1, Jan 2020.

  • S. Kalra, "On the mathematical insight of moderate inversion for ultradeep submicron CMOS technologies," Journal of Computational Electronics, vol. 15, pp. 1-5, 2018.

  • S. Kalra and A.B. Bhattacharyya, "Scalable α-power law based MOSFET model for characterization of ultra deep submicron digital integrated circuit design," AEU-International Journal of Electronics and Communications, vol. 83, no. 1, pp. 180-187, 2018.

  • S. Kalra and A. Bhattacharyya, "Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold," International Journal of Electronics and Telecommunications, vol. 63, no. 4, pp. 369-374, 2017.

  • S. Sharma and S. Kalra, "Study of Temperature Dependent Ultra Low Power Deep Submicron Digital CMOS Logic," Journal of Energy Research and Environmental Technology (JERET), vol. 4, no. 1, pp. 29-31, 2017.

  • N. Narula and S. Kalra, "High Performance Low Power Arithmetic and Logic Unit: A Trade off," Journal of Energy Research and Environmental Technology (JERET), vol. 4, no. 1, pp. 23-28, 2017.

  • S. Kalra and A. B. Bhattacharyya, "An Analytical Study Of Temperature Dependence of Scaled CMOS Digital Circuits Using α–Power MOSFET Model," Journal of Integrated Circuits and System, vol. 11, no. 1, pp. 57-68, 2016.

  • S. Kalra, " An Insight into Temperature Inversion Using α-Power MOSFET Model for Ultradeep Submicron Digital CMOS Technologies", AEU-International Journal of Electronics and Communications, vol. 125, p.153349, July 2020 .
  • S. Kalra and A.B. Bhattacharyya, "A Unified Analytical Transregional MOSFET Model for Nanoscale CMOS Digital Technologies", International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol 33, issue 1, Jan 2020.
  • S. Kalra,"On the mathematical insight of moderate inversion for ultradeep submicron CMOS technologies", Journal of Computational Electronics, vol. 15, pp 1-5, 2018.
  • Kalra S, A.B. Bhattacharyya,“Scalable α-power law based MOSFET model for characterization of ultra deep submicron digital integrated circuit design”, AEU-International Journal of Electronics and Communications,vol. 83 no. 1, pp 180-187, 2018.
  • S. Kalra and A. Bhattacharyya, “Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold,” International Journal of Electronics and Telecommunications, vol. 63, no. 4, pp. 369-374, 2017. 
  • Sharma, S. Kalra,”Study of Temperature Dependent Ultra Low Power Deep Submicron Digital CMOS Logic”, Journal of Energy Research and Environmental Technology(JERET), vol 4, no.1, pp. 29-31, 2017.
  • N. Narula, S. Kalra,”High Performance Low Power Arithmetic and Logic Unit: A Trade off”, Journal of Energy Research and Environmental Technology (JERET), vol 4, no.1, pp. 23-28, 2017.
  • S. Kalra, A. B. Bhattacharyya, "An Analytical Study Of Temperature Dependence of Scaled CMOS Digital Circuits Using α–Power MOSFET Model." Journal of Integrated Circuits and System, vol. 11, no. 1, pp. 57-68, 2016.

Conferences:

  • P. Singh, A. Noor, and S. Sabharwal, "Utilizing transaction level modeling in systemC to model serial interfaces," in Proceedings of 2nd national conference Mathematical techniques: Emerging paradigms for electronics and IT industries, Sep. 2008, pp. 26th-28th.

  • S. Sabharwal and A. Noor, "An area efficient Implementation of Reed-Solomon Encoder for DVB-H Protocol," in Proceedings of 2nd national conference of resent trends in information systems (RETIS-2008), Jadavpur University Calcutta, 7-9 Feb 2008.

  • S. M. Hasnain, N. Ahuja, A. Noor, and S. Sabharwal, "Comparative Analysis of Subthreshold Leakage Reduction techniques using stack and VTCMOS technique" in Proceedings of National conference on modern trends in electronics and communication systems (MTECS-2008), AMU, Aligarh, 8-9th March 2008.

  • N. Gupta, R. Tripathi, and S. Sabharwal, "Design Methodology of standard cell library for sub-micron technology," in Proceedings of 4th National Conference on VLSI, Embedded System, Signal Processing and Communication Technologies, April 2011.

  • S. Kalra, "Effect of temperature dependence on performance of Digital CMOS circuit technologies," in International Conference on Signal Processing and Communication (ICSC-2013), Dec. 12-14, 2013, JIIT NOIDA, India.

  • S. Kalra, "A Graphical Insight into α Power MOSFET Model for Nanoscale CMOS Digital Technologies," in 2020 IEEE 6th International Conference on Signal Processing and Communication (ICSC), Noida, India, 2020, pp. 325-330.

  • K. Singh and S. Kalra, "A Comprehensive Assessment of Current Trends in Negative Bias Temperature Instability (NBTI) Deterioration," in 2021 7th International Conference on Signal Processing and Communication (ICSC), pp. 271-276, IEEE, 2021.

  • S. Tripathi, A. Dudhane, and S. Kalra, "An Autonomous Electronic Zoological Feeder," in 2021 7th International Conference on Signal Processing and Communication (ICSC), pp. 286-291, IEEE, 2021.

  • A. Saini, G. Kundra, and S. Kalra, "A survey on hardware trojan detection: Alternatives to destructive reverse engineering," in Proceedings of Second International Conference on Computing, Communications, and Cyber-Security, pp. 885-897, Springer, Singapore, 2021.

  • K. Singh and S. Kalra, "Analysis of Negative-Bias Temperature Instability Utilizing Machine Learning Support Vector Regression for Robust Nanometer Design," in 2022 8th International Conference on Signal Processing and Communication (ICSC), pp. 571-577, IEEE, 2022.

  • V. Sharma, N. Singh, and S. Kalra, "Robust Prediction of Copy-Move Forgeries using Dual-Tree Complex Wavelet Transform and Principal Component Analysis," in 2022 8th International Conference on Signal Processing and Communication (ICSC), pp. 491-497, IEEE, 2022.

  • K.T. Adhitya and S. Kalra, "Gaming for Better Psychological Health: A Solution Based on the FPGA Zynq 7000," in 2022 8th International Conference on Signal Processing and Communication (ICSC), pp. 602-607, IEEE, 2022.

  • K. Singh, S. Kalra, and R. Beniwal, "Quantifying NBTI Recovery and Its Impact on Lifetime Estimations in Advanced Semiconductor Technologies," in 2023 9th International Conference on Signal Processing and Communication (ICSC), pp. 763-768, IEEE, 2023.

  • B. Gupta, R. Beniwal, S. Kalra, and P. Sharma, "Driving into the Future: A Comparative Analysis of the Hough Transform and Convolutional Neural Network for Autonomous Vehicles," in 2023 9th International Conference on Signal Processing and Communication (ICSC), pp. 302-308, IEEE, 2023.

Book Chapter

  • Kalra S, Bhattacharyya AB,“Variability Study Using α-Power-Based MOSFET Model for Ultradeep Submicron Digital Circuit Design”,  InAdvances in Signal Processing and Communication 2019 (pp. 601-610). Springer, Singapore.
  • K. Singh and S. Kalra, "VLSI Computer Aided Design Using Machine Learning for Biomedical Applications," in Opto-VLSI Devices and Circuits for Biomedical and Healthcare Applications, pp. 177-196, CRC Press, 2023.

Patents Filed:

PAN 202111005100; ERROR DETECTING PEN

PAN 202211036251; A METHODOLOGY FOR SMART GREENHOUSE BASED MONITORING AND ANALYZING THE HEALTH OF WILD ANIMALS

Professional Projects / Professional Achievements

Title of Research Project: Mixed Signal test structures for CMOS Temperature sensor using Mentor Graphics Design Environment.

Details of Sponsoring Agency : MENTOR GRAPHICS India

Sanction Date: March 2012

Completion Date: Aug 2015

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